SmartDV's high-quality standard protocol Design and Verification IP is used for simulation, emulation, field-programmable gate array (FPGA) prototyping, post-silicon validation, formal property verification, and RISC-V CPU verification.
SmartDV can rapidly customize all the Design and Verification IP to meet specific customer design needs. The result is Proven and Trusted in hundreds of communication, networking, storage, automotive, avionics, audio/video projects throughout the global electronics industry.
A number of ASICs with RapidIO LP-LVDS and 1x/4x LP-SERIAL interfaces has been released that include CPUs, switch and bridge devices. Based on these ASICs high-performance computing systems were built for industrial applications.
The latest RapidIO specification is always used for products under development.
The Computer Architecture and Systems group of the CSE department is one of the leading research groups in High performance Computing, Processor architecture and VLSI Engineering.