2015 HEART Technical Interchange Meeting (TIM)

Updated HEART 2015 TIM Banner

April 20-24, 2015
Westfields Marriott
Chantilly, Virginia
Event Information »

This year, the 2015 Hardened Electronics and Radiation Technology (HEART) Technical Interchange Meeting (TIM) will be held in Chantilly, Virginia, home of The Aerospace Corporation conference center.

Join RapidIO.org members AFRL, Mobiveil, Texas Instruments, FET Corp and Mirabilis Design at the 2015 HEART Conference at booth #10.

  • Mobiveil will be providing information about their Gen2 and Gen 3(10xN) RapidIO IP blocks.
    • GRIO- Mobiveil Generic RapidIO (GRIO) controller is a highly flexible and configurable IP to provide RapidIO interface on one side and a generic interface on the system side. The Mobiveil Generic RapidIO Controller Solution can be used as a Host or device. The controller architecture is carefully tailored to optimize link utilization, latency, reliability, power consumption, and silicon footprint. Mobiveil Generic RapidIO Controller design is fully synchronous and adheres to standard synthesis, test insertion and physical design practices.
    • RapidIO-AXI Bridge- Mobiveil RapidIO-AXI Bridge (RIO-AXI Bridge) is a highly flexible and configurable IP with a RapidIO interface on one side and an AXI interface on the system side. The Bridge has been architected to interface with a RapidIO controller used as a Host or device. The RapidIO-AXI BRIDGE uses high speed multi-channel DMA and Message controllers to match the bandwidth requirements of the RapidIO solution
  • TI will display the HP ProLiant m800 which is the highest density DSP solution in an industry standard infrastructure in the market today, with 1,440 DSP cores, 720 ARM cores and up to 11.5TB of storage in a single Moonshot chassis. The platform delivers low latency at lower cost and power built on the HP Moonshot innovative 2D Torus Fabric combined with Texas Instrument’s built-in RapidIO unified fabric.
  • FET Corp will demo RapidFET Probe2.0 which is the latest in RapidFET Probe technology that provides the ability to support 1.25, 2.5, 3.125, 5.0, and 6.25 Gpbs connections providing diagnostic, interoperability testing, and network management features for many of the RapidIO processor and FPGA based systems that are available today.
  • Mirabilis Design will demo verification of FPGA-based implementation using a virtual network model: Connect the hardware implementation on a Xilinx Zynq7000 FPGA board to a RapidIO backplane that is on a 1 Gbps Ethernet network virtual model. This demo will show how systems implemented on FPGA boards can be verified against a variety of realistic network architectures.