Third generation of standard builds on wireless and embedded markets, poised for expansion in supercomputing and servers.
Taipei, Taiwan – October 28, 2013 – The RapidIO® Trade Association (RTA), dedicated to driving the development and adoption of the RapidIO interconnect standard, today announced the release of the RapidIO 10xN Standard, which is the third generation of the RapidIO Technology Specifications. Driven by the members which include the world’s leading embedded market OEM’s and Suppliers, the goal was to further enhance the specification by enabling additional high speed link implementations and broaden the market applications. Today RapidIO is deployed in most high performance embedded multi processor systems. With the RapidIO 10xN specification RapidIO will have the opportunity to expand beyond its early adopters in Supercomputing and Servers.
The 10xN specification, backward compatible with RapidIO Gen1 and Gen2 systems, supports 10.3125 Gbaud per serial lane with lane widths of x1, x2, x4, x8 and x16, resulting in data rates up to 160 Gbps per port direction. The standard leverages Ethernet 10GBASE-KR electrical specifications for short (20cm + connector) and long (1m + 2 connector) reach applications and uses the Ethernet 10GBASE-KR DME training scheme for long reach signal quality optimization. The encoding scheme substantially reduces overhead by going with a 64b/67b encoding scheme, similar to the Interlaken standard, to support both copper and optical interconnects and improve efficiency. Other features include dynamic asymmetric links to save power (i.e. 4x in one direction, 1x in the other), addition of IEEE 1588 PTP-like time synchronization capabilities, support for 32 bit device IDs, increasing maximum network size and enabling innovative hardware virtualization support. The full specification may be downloaded at http://rapidio.wpengine.com/specs/current/.
“RapidIO is the primary base station interconnect standard used in current 4G deployments and has proliferated into a variety of embedded markets ranging from aerospace and defense to medical imaging and industrial automation,” said RapidIO Trade Association Steering Committee Chairman Paul Carson of Texas Instruments. “Our member companies have driven innovation in RapidIO to release the 10xN version of that standard to grow in these markets and to build in Data Center and Supercomputing markets from the early adopters we have today. Our reference designs for the RapidIO Data Center Compute and Networking task group will also leverage future RapidIO 10xN solutions.”
In addition to the RapidIO 10xN specification, the RTA is developing an updated Bus Functional Model. The BFM provides interoperability and compliance checking and is supplied as a modular behavioral C model and to provide a set of features and functions for simulating and verifying RapidIO systems of arbitrary complexity. The BFM is available to RapidIO Trade Association members in source code or object code form and is designed as a flexible tool for the development, evaluation and verification of RapidIO interface products. For more information visit http://rapidio.wpengine.com/education/documents/RTA_BFM_documentation.pdf
Technology Roadmap Development
Beyond the RapidIO 10xN specification and the full series of Gen3 specifications the RTA is also kicking off the development of the next generation with data rates scaling up to 25 Gbps per serial lane. Industry participation is requested by silicon, systems and software vendors and is available to all sponsoring, regular and steering members of the RapidIO Trade Association.
About the RapidIO Standard
The RapidIO standard is the multi processor interconnect developed by an open standards based community for the embedded and computing communities. This ISO-certified, open-standard enables best-in-class quality of service and performance in multi-processor peer to peer applications – from components to systems – that require reliable, low power, high speed, cost-effective connectivity. The RapidIO interconnect standard seamlessly enables the chip-to-chip, board-to-board, control, backplane and data plane interconnections needed in high-performance networking, communications and embedded systems.
About the RapidIO Trade Association:
The RapidIO Trade Association, a non-profit corporation controlled by its members, directs the future development and drives the adoption of the RapidIO architecture. The RapidIO architecture promises lower-latency, increased bandwidth efficiency, lower cost and lower power. Interested companies are invited to join the RapidIO Trade Association to gain access to the standards development process. Detailed information on the RapidIO specification, products, design tools, member companies, and membership is available at www.RapidIO.org.