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HDL Design House specializes in rendering design and verification services for SoC projects and providing soft IP cores and verification IP (VIP) based on advanced ...
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News & Articles02 Oct 2008: Curtiss-Wright's New 3U VPX Virtex®-5 XMC Card Delivers Rugged High Performance Small Form Factor FPGA Computing 30 Sep 2008: VMETRO combines the power of fiber-optics with Xilinx Virtex-5 FPGAs in an XMC module 29 Sep 2008: OBSAI forum and RapidIO Trade Association partnership enables double speed in RP3 standard 25 Sep 2008: VMETRO continues VPX momentum with addition of 3U VITA 46 FPGA Processing Engine |
Events & EducationRapidIO® Radio's "Interoperability Testing and the RapidIO® Standard: The Need for Repeatable and Quantitative Assessment" identifies three key implementation challenges that often affect device interoperability.The podcast provides embedded designers with a detailed analysis of types of interoperability and the critical need for repeatability in testing that will prove invaluable as they specify devices for next-generation applications. Download RapidIO Radio Episode 9 (6.2 MB; 16:03). |
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